Field
Embodiments of the present disclosure generally relate to manufacturing processes, and more particularly to techniques for predicting the topography of a product produced from a manufacturing process.
Description of the Related Art
In many manufacturing industries, the geometry of devices continues to decrease in size since such devices were first introduced several decades ago. In semiconductor manufacturing, for example, integrated circuits have generally followed “Moore's Law,” which states that a number of devices fitting on a chip will double every two years. As the demand for higher yield devices is expected to increase further yet, the need to achieve high-yield, high quality devices has prompted issues not previously considered to emerge as areas of concern. One such issue relates to the topography of a product produced from a manufacturing process.
Generally, in manufacturing, the topography of a product that results from production is often a key factor that relates to the quality and/or yield of the product. For example, in semiconductor manufacturing, many processes (e.g., such as deposition, etching, oxidation, etc.) used in the fabrication of semiconductor devices can result in changes in the shape and/or composition of a wafer surface. Such changes, in turn, can result in significant differences in yield of the product (e.g., the number of good die on the wafer), final feature quality of the product (e.g., aspect ratio or some other quality associated with features, such as trenches, contact holes, vias, etc.), and/or performance of the product (e.g., insulating properties, etc.). As such, improved control over the resulting topography of a product produced from a manufacturing process is necessary to ensure that the final product does not have low yield, low quality, and/or low performance.
Currently in manufacturing, topography and its impact is typically assessed post-process. For example, conventional techniques typically rely on yield management systems, post-process, to detect potential yield issues with a resulting product (e.g., detecting whether a percentage yield loss is present in the product). Once the issues are identified, the conventional techniques rely on data mining to identify the processes and/or process settings that should be adjusted. Assessing topography, however, in this manner is extremely inefficient and time-consuming. For example, closing the loop (e.g., finding the optimal process settings, processes, etc.) can often take weeks, during which significant quality reduction and/or yield loss can occur until the problem is identified, appropriate corrective action is determined, and the corrective action is implemented.
In addition, other conventional techniques that attempt to address the above issues typically perform post-process metrology data monitoring and mining to identify topographical anomalies and relate the identified anomalies to processing issues in the manufacturing process. These techniques, however, are also inefficient at correcting any identified problems, as these techniques are post-process techniques and as such do not prevent the current product (e.g., wafer lot, etc.) from having low yield, quality, or performance. For example, with these techniques, once topographical anomalies are identified, the techniques typically rely on manual (or human guided) methods to correct parameters of the current process (and possibly upstream processes) to reduce the problem for future wafers. However, performing a correction process in this manner leads to inexact results (e.g., due to human error), is not always immediate, and is incapable of improving yield of the current product or product lot.